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Title: | Enhanced Drain Current of 4H-SiC MOSFETs by Adopting a Three-Dimensional Gate Structure |
Authors: | Nanen, Yuichiro Yoshioka, Hironori Noborio, Masato Suda, Jun Kimoto, Tsunenobu https://orcid.org/0000-0002-6649-2090 (unconfirmed) |
Keywords: | Metal-oxide-semiconductor field-effect transistor (MOSFET) multigate FET (MuGFET) silicon carbide (SiC) 3-D gate structure |
Issue Date: | Nov-2009 |
Publisher: | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
Journal title: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
Volume: | 56 |
Issue: | 11 |
Start page: | 2632 |
End page: | 2637 |
Abstract: | 4H-SiC (0001) metal-oxide-semiconductor field-effect transistors (MOSFETs) with a 3-D gate structure, which has a top channel on the (0001) face and side-wall channels on the {112macr0} face, have been fabricated. The 3-D gate structures with a 1-5-mum width and a 0.8- mum height have been formed by reactive ion etching, and the gate oxide has been deposited by plasma-enhanced chemical vapor deposition and then annealed in N2O ambient at 1300degC. The fabricated MOSFETs have exhibited good characteristics: The I ON/I OFF ratio, the subthreshold swing, and V TH are 109, 210 mV/decade, and 3.5 V, respectively. The drain current normalized by the gate width is increasing with decreasing the gate width. The normalized drain current of a 1-mum-wide MOSFET is 16 times higher than that of a conventional planar MOSFET. |
Rights: | © 2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
URI: | http://hdl.handle.net/2433/109802 |
DOI(Published Version): | 10.1109/TED.2009.2030437 |
Appears in Collections: | Journal Articles |
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