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Title: A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits
Authors: KAWASHIMA, Junya
TSUTSUI, Hiroshi
OCHI, Hiroyuki
SATO, Takashi  kyouindb  KAKEN_id  orcid https://orcid.org/0000-0002-1577-8259 (unconfirmed)
Author's alias: 川島, 潤也
佐藤, 高史
Keywords: subthreshold operation
process variation
minimum operation voltage estimation
energy minimization
yield maximization
Issue Date: Dec-2012
Publisher: Institute of Electronics, Information and Communication Engineers
Journal title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume: E95.A
Issue: 12
Start page: 2242
End page: 2250
Abstract: We investigate a design strategy for subthreshold circuits focusing on energy-consumption minimization and yield maximization under process variations. The design strategy is based on the following findings related to the operation of low-power CMOS circuits: (1) The minimum operation voltage (VDDmin) of a circuit is dominated by flip-flops (FFs), and VDDmin of an FF can be improved by upsizing a few key transistors, (2) VDDmin of an FF is stochastically modeled by a log-normal distribution, (3) VDDmin of a large circuit can be efficiently estimated by using the above model, which eliminates extensive Monte Carlo simulations, and (4) improving VDDmin may substantially contribute to decreasing energy consumption. The effectiveness of the proposed design strategy has been verified through circuit simulations on various circuits, which clearly show the design tradeoff between voltage scaling and transistor sizing.
Rights: © 2012 The Institute of Electronics, Information and Communication Engineers
URI: http://hdl.handle.net/2433/174335
DOI(Published Version): 10.1587/transfun.E95.A.2242
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