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Title: Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element
Authors: YUASA, Hiroshi
TSUTSUI, Hiroshi
OCHI, Hiroyuki
SATO, Takashi  kyouindb  KAKEN_id
Author's alias: 佐藤, 高史
Keywords: statistical static timing analysis
delay distribution
slew rate
field-programmable gate array
Mersenne Twister
Issue Date: Apr-2013
Publisher: The Institute of Electronics, Information and Communication Engineers
Journal title: IEICE Transactions on Electronics
Volume: E96.C
Issue: 4
Start page: 473
End page: 481
Abstract: We propose a novel acceleration scheme for Monte Carlo based statistical static timing analysis (MC-SSTA). MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference. A large number of random samples, however, should be processed to obtain accurate delay distributions, and software implementation of MC-SSTA, therefore, takes an impractically long processing time. In our approach, a generalized hardware module, the STA processing element (STA-PE), is used for the delay evaluation of a logic gate, and netlist-specific information is delivered in the form of instructions from an SRAM. Multiple STA-PEs can be implemented for parallel processing, while a larger netlist can be handled if only a larger SRAM area is available. The proposed scheme is successfully implemented on Altera's Arria II GX EP2AGX125EF35C4 device in which 26 STA-PEs and a 624-port Mersenne Twister-based random number generator run in parallel at a 116MHz clock rate. A speedup of far more than ×10 is achieved compared to conventional methods including GPU implementation
Rights: © 2013 The Institute of Electronics, Information and Communication Engineers
URI: http://hdl.handle.net/2433/178693
DOI(Published Version): 10.1587/transele.E96.C.473
Related Link: http://www.ieice.org/jpn/index.html
Appears in Collections:Journal Articles

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