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Title: A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis
Authors: IMAGAWA, Takashi
TSUTSUI, Hiroshi
OCHI, Hiroyuki
SATO, Takashi  kyouindb  KAKEN_id  orcid (unconfirmed)
Author's alias: 今川, 隆司
佐藤, 高史
Keywords: soft error
single event upset
triple modular redundancy
simulated annealing
Issue Date: Apr-2013
Publisher: The Institute of Electronics, Information and Communication Engineers
Journal title: IEICE Transactions on Electronics
Volume: E96.C
Issue: 4
Start page: 454
End page: 462
Abstract: This paper proposes a novel method to determine a priority for applying selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of application circuits onto coarse-grained reconfigurable architectures (CGRAs). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) of the application circuit. The estimation is based on a weighted sum of the node parameters which characterize impact of the SEU in the node on the output data. This method does not require time-consuming placement-and-routing processes, as well as extensive fault simulations for various triplicating patterns, which allows us to identify the set of nodes to be triplicated for minimizing the vulnerability under given area constraint at the early stage of design flow. Therefore, the proposed method enables us efficient design space exploration of reliability-oriented CGRAs and their applications.
Rights: © 2013 The Institute of Electronics, Information and Communication Engineers
DOI(Published Version): 10.1587/transele.E96.C.454
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