Downloads: 261

Files in This Item:
File Description SizeFormat 
transfun.E93.A.2409.pdf1.01 MBAdobe PDFView/Open
Title: Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence
Authors: HAGIWARA, Shiho
MASU, Kazuya
SATO, Takashi  kyouindb  KAKEN_id  orcid (unconfirmed)
Author's alias: 佐藤, 高史
Keywords: capacitance
power distribution network
integrated circuit modeling
electromagnetic interference
Issue Date: Dec-2010
Publisher: The Institute of Electronics, Information and Communication Engineers
Journal title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume: E93-A
Issue: 12
Start page: 2409
End page: 2416
Abstract: A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The maximum and minimum capacitances are also calculated using average and variance estimation. Calculation times are linear time-complexity, too. The proposed tool facilitates to build an accurate macro model of an LSI.
Rights: © 2010 The Institute of Electronics, Information and Communication Engineers
DOI(Published Version): 10.1587/transfun.E93.A.2409
Related Link:
Appears in Collections:Journal Articles

Show full item record

Export to RefWorks

Export Format: 

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.