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Title: Device-Parameter Estimation through IDDQ Signatures
Authors: SHINTANI, Michihiro
SATO, Takashi  kyouindb  KAKEN_id  orcid (unconfirmed)
Author's alias: 新谷, 道広
佐藤, 高史
Keywords: IDDQ testing
statistical leakage current analysis
Bayes' theorem
Issue Date: Feb-2013
Publisher: The Institute of Electronics, Information and Communication Engineers
Journal title: IEICE Transactions on Information and Systems
Volume: E96.D
Issue: 2
Start page: 303
End page: 313
Abstract: We propose a novel technique for the estimation of device-parameters suitable for postfabrication performance compensation and adaptive delay testing, which are effective means to improve the yield and reliability of LSIs. The proposed technique is based on Bayes' theorem, in which the device-parameters of a chip, such as the threshold voltage of transistors, are estimated by current signatures obtained in a regular IDDQ testing framework. Neither additional circuit implementation nor additional measurement is required for the purpose of parameter estimation. Numerical experiments demonstrate that the proposed technique can achieve 10-mV accuracy in threshold voltage estimations.
Rights: © 2013 The Institute of Electronics, Information and Communication Engineers
DOI(Published Version): 10.1587/transinf.E96.D.303
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