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ファイル | 記述 | サイズ | フォーマット | |
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transele.E97.C.77.pdf | 2.25 MB | Adobe PDF | 見る/開く |
タイトル: | State-Dependence of On-Chip Power Distribution Network Capacitance |
著者: | YAMANAGA, Koh HAGIWARA, Shiho TAKAHASHI, Ryo MASU, Kazuya SATO, Takashi ![]() ![]() ![]() |
著者名の別形: | 佐藤, 高史 |
キーワード: | CMOS logic circuit state-dependent capacitance model capacitance measurement PDN-capacitance parasitic capacitance |
発行日: | Jan-2014 |
出版者: | Institute of Electronics, Information and Communication Engineers(IEICE) |
誌名: | IEICE Transactions on Electronics |
巻: | E97.C |
号: | 1 |
開始ページ: | 77 |
終了ページ: | 84 |
抄録: | In this paper, the measurement of capacitance variation, of an on-chip power distribution network (PDN) due to the change of internal states of a CMOS logic circuit, is studied. A state-dependent PDN-capacitance model that explains measurement results will be also proposed. The model is composed of capacitance elements related to MOS transistors, signal and power supply wires, and substrate. Reflecting the changes of electrode potentials, the capacitance elements become state-dependent. The capacitive elements are then all connected in parallel between power supply and ground to form the proposed model. By using the proposed model, state-dependence of PDN-capacitances for different logic circuits are studied in detail. The change of PDN-capacitance exceeds 12% of its total capacitance in some cases, which corresponds to 6% shift of anti-resonance frequency. Consideration of the state-dependence is important for modeling the PDN-capacitance. |
著作権等: | © 2014 The Institute of Electronics, Information and Communication Engineers |
URI: | http://hdl.handle.net/2433/179967 |
DOI(出版社版): | 10.1587/transele.E97.C.77 |
出現コレクション: | 学術雑誌掲載論文等 |

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