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Title: State-Dependence of On-Chip Power Distribution Network Capacitance
Authors: YAMANAGA, Koh
MASU, Kazuya
SATO, Takashi  kyouindb  KAKEN_id  orcid (unconfirmed)
Author's alias: 佐藤, 高史
Keywords: CMOS logic circuit
state-dependent capacitance model
capacitance measurement
parasitic capacitance
Issue Date: Jan-2014
Publisher: Institute of Electronics, Information and Communication Engineers(IEICE)
Journal title: IEICE Transactions on Electronics
Volume: E97.C
Issue: 1
Start page: 77
End page: 84
Abstract: In this paper, the measurement of capacitance variation, of an on-chip power distribution network (PDN) due to the change of internal states of a CMOS logic circuit, is studied. A state-dependent PDN-capacitance model that explains measurement results will be also proposed. The model is composed of capacitance elements related to MOS transistors, signal and power supply wires, and substrate. Reflecting the changes of electrode potentials, the capacitance elements become state-dependent. The capacitive elements are then all connected in parallel between power supply and ground to form the proposed model. By using the proposed model, state-dependence of PDN-capacitances for different logic circuits are studied in detail. The change of PDN-capacitance exceeds 12% of its total capacitance in some cases, which corresponds to 6% shift of anti-resonance frequency. Consideration of the state-dependence is important for modeling the PDN-capacitance.
Rights: © 2014 The Institute of Electronics, Information and Communication Engineers
DOI(Published Version): 10.1587/transele.E97.C.77
Appears in Collections:Journal Articles

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