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Title: An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs
Authors: IMAGAWA, Takashi
HIROMOTO, Masayuki  kyouindb  KAKEN_id
OCHI, Hiroyuki
SATO, Takashi  kyouindb  KAKEN_id  orcid https://orcid.org/0000-0002-1577-8259 (unconfirmed)
Author's alias: 佐藤, 高史
Keywords: coarse-grained reconfigurable architecture
reliability
triple modular redundancy
immediate termination
error-critical period
Issue Date: Jul-2015
Publisher: Institute of Electronics, Information and Communication Engineers(IEICE)
Journal title: IEICE Transactions on Electronics
Volume: E98.C
Issue: 7
Start page: 741
End page: 750
Abstract: Time redundancy is sometimes an only option for enhancing circuit reliability when the circuit area is severely restricted. In this paper, a time-redundant error-correction scheme, which is particularly suitable for coarse-grained reconfigurable arrays (CGRAs), is proposed. It judges the correctness of the executions by comparing the results of two identical runs. Once a mismatch is found, the second run is terminated immediately to start the third run, under the assumption that the errors tend to persist in many applications, for selecting the correct result in the three runs. The circuit area and reliability of the proposed method is compared with a straightforward implementation of time-redundancy and a selective triple modular redundancy (TMR). A case study on a CGRA revealed that the area of the proposed method is 1% larger than that of the implementation for the selective TMR. The study also shows the proposed scheme is up to 2.6x more reliable than the full-TMR when the persistent error is predominant.
Rights: © 2015 The Institute of Electronics, Information and Communication Engineers
URI: http://hdl.handle.net/2433/198743
DOI(Published Version): 10.1587/transele.E98.C.741
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