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Title: Fast estimation of NBTI-induced delay degradation based on signal probability
Authors: Bian, Song
Shintani, Michihiro
Hiromoto, Masayuki  kyouindb  KAKEN_id
Sato, Takashi  kyouindb  KAKEN_id
Author's alias: 新谷, 道広
廣本, 正之
佐藤, 高史
Keywords: NBTI
static timing analysis
timing characterization
aging-aware timing library
Issue Date: 1-Jul-2016
Publisher: Institute of Electronics, Information and Communication Engineers(IEICE)
Journal title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume: E99.A
Start page: 1400
End page: 1409
Abstract: As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. Hence, taking aging-induced degradation into account during the design phase can greatly improve the reliability of the manufactured devices. However, accurately estimating the aging effect for extremely large circuits, like processors, is time-consuming. In this research, we focus on the negative bias temperature instability (NBTI) as the aginginduced degradation mechanism, and propose a fast and efficient way of estimating NBTI-induced delay degradation by utilizing static-timing analysis (STA) and simulation-based lookup table (LUT). We modeled each type of gates at different degradation levels, load capacitances and input slews. Using these gate-delay models, path delays of arbitrary circuits can be efficiently estimated. With a typical five-stage pipelined processor as the design target, by comparing the calculated delay from LUT with the reference delay calculated by a commercial circuit simulator, we achieved 4114 times speedup within 5.6% delay error.
Rights: © 2016 The Institute of Electronics, Information and Communication Engineers.
DOI(Published Version): 10.1587/transfun.E99.A.1400
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