Downloads: 236

Files in This Item:
File Description SizeFormat 
transfun.E100.A.1464.pdf651.58 kBAdobe PDFView/Open
Title: Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation
Authors: MORITA, Shumpei
BIAN, Song  kyouindb  KAKEN_id
SHINTANI, Michihiro
HIROMOTO, Masayuki  kyouindb  KAKEN_id
SATO, Takashi  kyouindb  KAKEN_id  orcid (unconfirmed)
Author's alias: 廣本, 正之
佐藤, 高史
Keywords: NBTI mitigation
transistor aging
performance degradation
internal node control
Issue Date: 1-Jul-2017
Publisher: Institute of Electronics, Information and Communications Engineers (IEICE)
Journal title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume: E100.A
Issue: 7
Start page: 1464
End page: 1472
Abstract: Replacement of highly stressed logic gates with internal node control (INC) logics is known to be an effective way to alleviate timing degradation due to NBTI. We propose a path clustering approach to accelerate finding effective replacement gates. Upon the observation that there exist paths that always become timing critical after aging, critical path candidates are clustered to select representative path in each cluster. With efficient data structure to further reduce timing calculation, INC logic optimization has first became tractable in practical time. Through the experiments using a processor, 171x speedup has been demonstrated while retaining almost the same level of mitigation gain.
Rights: © 2017 The Institute of Electronics, Information and Communication Engineers
DOI(Published Version): 10.1587/transfun.E100.A.1464
Appears in Collections:Journal Articles

Show full item record

Export to RefWorks

Export Format: 

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.