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タイトル: Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation
著者: MORITA, Shumpei
BIAN, Song  KAKEN_id
SHINTANI, Michihiro
HIROMOTO, Masayuki  KAKEN_id
SATO, Takashi  kyouindb  KAKEN_id  orcid https://orcid.org/0000-0002-1577-8259 (unconfirmed)
著者名の別形: 廣本, 正之
佐藤, 高史
キーワード: NBTI mitigation
reliability
transistor aging
performance degradation
internal node control
発行日: 1-Jul-2017
出版者: Institute of Electronics, Information and Communications Engineers (IEICE)
誌名: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
巻: E100.A
号: 7
開始ページ: 1464
終了ページ: 1472
抄録: Replacement of highly stressed logic gates with internal node control (INC) logics is known to be an effective way to alleviate timing degradation due to NBTI. We propose a path clustering approach to accelerate finding effective replacement gates. Upon the observation that there exist paths that always become timing critical after aging, critical path candidates are clustered to select representative path in each cluster. With efficient data structure to further reduce timing calculation, INC logic optimization has first became tractable in practical time. Through the experiments using a processor, 171x speedup has been demonstrated while retaining almost the same level of mitigation gain.
著作権等: © 2017 The Institute of Electronics, Information and Communication Engineers
URI: http://hdl.handle.net/2433/226311
DOI(出版社版): 10.1587/transfun.E100.A.1464
出現コレクション:学術雑誌掲載論文等

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