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Title: Identification and Application of Invariant Critical Paths under NBTI Degradation
Authors: BIAN, Song
MORITA, Shumpei
SHINTANI, Michihiro
AWANO, Hiromitsu
HIROMOTO, Masayuki  kyouindb  KAKEN_id
SATO, Takashi  kyouindb  KAKEN_id
Author's alias: 辺, 松
森田, 俊平
新谷, 道広
粟野, 皓光
廣本 , 正之
佐藤, 高史
Keywords: NBTI
aging effect
invariant critical path
processor
Issue Date: Dec-2017
Publisher: Institute of Electronics, Information and Communications Engineers (IEICE)
Journal title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume: E100.A
Issue: 12
Start page: 2797
End page: 2806
Abstract: As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) are known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and propose a two-stage path extraction algorithm to identify the invariant critical paths (ICPs) in the processor. Utilizing these paths, we also propose an optimization technique for the replacement of internal node control logic that mitigates the NBTI degradation in the design. Through numerical experiment on two processor designs, we achieved nearly 300x reduction in the sheer number of paths on both designs. Utilizing the extracted ICPs, we achieved 96x-197x speedup without loss in mitigation gain.
Rights: © 2017 The Institute of Electronics, Information and Communication Engineers
URI: http://hdl.handle.net/2433/229140
DOI(Published Version): 10.1587/transfun.E100.A.2797
Related Link: http://www.ieice.org/jpn/index.html
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