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Title: Area Efficient Annealing Processor for Ising Model without Random Number Generator
Authors: GYOTEN, Hidenori
HIROMOTO, Masayuki  kyouindb  KAKEN_id
SATO, Takashi  kyouindb  KAKEN_id
Author's alias: 業天, 英範
廣本 , 正之
佐藤, 高史
Keywords: combinatorial optimization problem
max-cut problem
Ising model
annealing
FPGA
Issue Date: Feb-2018
Publisher: Institute of Electronics, Information and Communications Engineers (IEICE)
Journal title: IEICE Transactions on Information and Systems
Volume: E101.D
Issue: 2
Start page: 314
End page: 323
Abstract: An area-efficient FPGA-based annealing processor that is based on Ising model is proposed. The proposed processor eliminates random number generators (RNGs) and temperature schedulers, which are the key components in the conventional annealing processors and occupying a large portion of the design. Instead, a shift-register-based spin flipping scheme successfully helps the Ising model from stucking in the local optimum solutions. An FPGA implementation and software-based evaluation on max-cut problems of 2D-grid torus structure demonstrate that our annealing processor solves the problems 10-10[4] times faster than conventional optimization algorithms to obtain the solution of equal accuracy.
Rights: © 2018 The Institute of Electronics, Information and Communication Engineers
URI: http://hdl.handle.net/2433/229141
DOI(Published Version): 10.1587/transinf.2017RCP0015
Related Link: http://www.ieice.org/jpn/index.html
Appears in Collections:Journal Articles

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