On the Design of the Kyoto University Digital Computer KDC-I

Abstract

This paper describes the outline, the design features and design problems of the KDC-I, Kyoto University Digital Computer I, which has been developed and built in collaboration with Hitachi, Ltd. and put into operation since August 1960 at the computation center of the University. Emphasis is laid on the computer instructions. On other subjects only main design features are given. The KDC-I is a serial-parallel decimal computer using transistor dynamic flip-flop circuits operating at 230kc per second. A magnetic core and magnetic drum memory constitute the main internal memory of the computer, while magnetic tape memory is used as an external memory. Both fixed-point and floating-point operations are feasible in the computer. The concurrent operations of the output and of the magnetic tape units with the central processing unit increase the processing speed of the computer. The programming group at the University has already completed a fairly extensive library of subroutines and some very useful assemblers such as SYCS-1. Moreover a KDC ALGOL 60 Compiler is now under program test. The KDC-I has already performed a vast amount of calculations on various problems, which have been submitted by the staff and students of the University. With two years of operating experience, satisfactory results are being obtained from this computer.