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タイトル: | Plasma-induced defect-site generation in si substrate and its impact on performance degradation in scaled MOSFETs |
著者: | Eriguchi, Koji ![]() ![]() ![]() Nakakubo, Yoshinori Matsuda, Asahiko Takao, Yoshinori Ono, Kouichi ![]() |
著者名の別形: | 江利口, 浩二 |
キーワード: | Capacitance Defect site Device simulation Drain current Plasma-induced damage (PID) |
発行日: | Dec-2009 |
出版者: | Institute of Electrical and Electronics Engineers (IEEE) |
誌名: | IEEE Electron Device Letters |
巻: | 30 |
号: | 12 |
開始ページ: | 1275 |
終了ページ: | 1277 |
論文番号: | 5313889 |
抄録: | Plasma-induced ion-bombardment damage was studied in terms of defect sites created underneath the exposed Si surface. From the shift of capacitancevoltage (C-V) curves, the defect sites were found to capture carriers (being negatively charged in the case of an Ar plasma exposure). This results in a change of the effective impurity-doping density and the profile. We also report that the defect density depends on the energy of ions from plasma. A simplified and quantitative model is proposed for the draincurrent degradation induced by the series-resistance increase by the damage. The relationship derived between the defect density and the draincurrent degradation is verified by device simulations. The proposed model is useful to predict the device performance change from plasma process parameters. |
著作権等: | c 2009 IEEE. |
URI: | http://hdl.handle.net/2433/89515 |
DOI(出版社版): | 10.1109/LED.2009.2033726 |
出現コレクション: | 学術雑誌掲載論文等 |

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