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Title: RSFQ 4-bit bit-slice integer multiplier
Authors: Tang, Guang Ming
Takagi, Kazuyoshi
Takagi, Naofumi  kyouindb  KAKEN_id
Author's alias: 高木, 一義
髙木, 直史
Keywords: multiplier
single-flux-quantum (SFQ)
superconducting integrated circuits
Issue Date: 1-Jun-2016
Publisher: Institute of Electronics, Information and Communication Engineers (IEICE)
Journal title: IEICE Transactions on Electronics
Volume: E99C
Issue: 6
Start page: 697
End page: 702
Abstract: A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-μm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n x 4n-bit multiplier consists of 2n + 17 stages. For verifying the algorithm and the logic design, a physical layout of the 8 x 8-bit multiplier has been designed with target operating frequency of 50 GHz and simulated. It consists of 21 stages and 11, 488 Josephson junctions. The simulation results show correct operation up to 62.5 GHz.
Rights: Copyright © 2016 The Institute of Electronics, Information and Communication Engineers.
DOI(Published Version): 10.1587/transele.E99.C.697
Appears in Collections:Journal Articles

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