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| ファイル | 記述 | サイズ | フォーマット | |
|---|---|---|---|---|
| transele.E99.C.697.pdf | 2.07 MB | Adobe PDF | 見る/開く |
| タイトル: | RSFQ 4-bit bit-slice integer multiplier |
| 著者: | Tang, Guang Ming Takagi, Kazuyoshi Takagi, Naofumi    https://orcid.org/0000-0003-0016-7436 (unconfirmed) |
| 著者名の別形: | 高木, 一義 髙木, 直史 |
| キーワード: | multiplier single-flux-quantum (SFQ) microprocessor superconducting integrated circuits |
| 発行日: | 1-Jun-2016 |
| 出版者: | Institute of Electronics, Information and Communication Engineers (IEICE) |
| 誌名: | IEICE Transactions on Electronics |
| 巻: | E99C |
| 号: | 6 |
| 開始ページ: | 697 |
| 終了ページ: | 702 |
| 抄録: | A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-μm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n x 4n-bit multiplier consists of 2n + 17 stages. For verifying the algorithm and the logic design, a physical layout of the 8 x 8-bit multiplier has been designed with target operating frequency of 50 GHz and simulated. It consists of 21 stages and 11, 488 Josephson junctions. The simulation results show correct operation up to 62.5 GHz. |
| 著作権等: | Copyright © 2016 The Institute of Electronics, Information and Communication Engineers. |
| URI: | http://hdl.handle.net/2433/226242 |
| DOI(出版社版): | 10.1587/transele.E99.C.697 |
| 出現コレクション: | 学術雑誌掲載論文等 |
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