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transfun.E100.A.2797.pdf | 1.14 MB | Adobe PDF | 見る/開く |
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dc.contributor.author | BIAN, Song | en |
dc.contributor.author | MORITA, Shumpei | en |
dc.contributor.author | SHINTANI, Michihiro | en |
dc.contributor.author | AWANO, Hiromitsu | en |
dc.contributor.author | HIROMOTO, Masayuki | en |
dc.contributor.author | SATO, Takashi | en |
dc.contributor.alternative | 辺, 松 | ja |
dc.contributor.alternative | 森田, 俊平 | ja |
dc.contributor.alternative | 新谷, 道広 | ja |
dc.contributor.alternative | 粟野, 皓光 | ja |
dc.contributor.alternative | 廣本 , 正之 | ja |
dc.contributor.alternative | 佐藤, 高史 | ja |
dc.date.accessioned | 2018-02-19T05:21:02Z | - |
dc.date.available | 2018-02-19T05:21:02Z | - |
dc.date.issued | 2017-12 | - |
dc.identifier.issn | 0916-8508 | - |
dc.identifier.uri | http://hdl.handle.net/2433/229140 | - |
dc.description.abstract | As technology further scales semiconductor devices, aging-induced device degradation has become one of the major threats to device reliability. In addition, aging mechanisms like the negative bias temperature instability (NBTI) are known to be sensitive to workload (i.e., signal probability) that is hard to be assumed at design phase. In this work, we analyze the workload dependence of NBTI degradation using a processor, and propose a novel technique to estimate the worst-case paths. In our approach, we exploit the fact that the deterministic nature of circuit structure limits the amount of NBTI degradation on different paths, and propose a two-stage path extraction algorithm to identify the invariant critical paths (ICPs) in the processor. Utilizing these paths, we also propose an optimization technique for the replacement of internal node control logic that mitigates the NBTI degradation in the design. Through numerical experiment on two processor designs, we achieved nearly 300x reduction in the sheer number of paths on both designs. Utilizing the extracted ICPs, we achieved 96x-197x speedup without loss in mitigation gain. | en |
dc.format.mimetype | application/pdf | - |
dc.language.iso | eng | - |
dc.publisher | Institute of Electronics, Information and Communications Engineers (IEICE) | en |
dc.publisher.alternative | 電子情報通信学会 | ja |
dc.rights | © 2017 The Institute of Electronics, Information and Communication Engineers | en |
dc.subject | NBTI | en |
dc.subject | aging effect | en |
dc.subject | invariant critical path | en |
dc.subject | processor | en |
dc.title | Identification and Application of Invariant Critical Paths under NBTI Degradation | en |
dc.type | journal article | - |
dc.type.niitype | Journal Article | - |
dc.identifier.jtitle | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | en |
dc.identifier.volume | E100.A | - |
dc.identifier.issue | 12 | - |
dc.identifier.spage | 2797 | - |
dc.identifier.epage | 2806 | - |
dc.relation.doi | 10.1587/transfun.E100.A.2797 | - |
dc.textversion | publisher | - |
dc.address | Department of Communications and Computer Engineering, School of Informatics, Kyoto University | en |
dc.address | Department of Communications and Computer Engineering, School of Informatics, Kyoto University | en |
dc.address | Department of Communications and Computer Engineering, School of Informatics, Kyoto University | en |
dc.address | Department of Communications and Computer Engineering, School of Informatics, Kyoto University | en |
dc.address | Department of Communications and Computer Engineering, School of Informatics, Kyoto University | en |
dc.address | Department of Communications and Computer Engineering, School of Informatics, Kyoto University | en |
dc.relation.url | http://www.ieice.org/jpn/index.html | - |
dcterms.accessRights | open access | - |
出現コレクション: | 学術雑誌掲載論文等 |
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