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| ファイル | 記述 | サイズ | フォーマット | |
|---|---|---|---|---|
| transinf.2016EDP7158.pdf | 512.37 kB | Adobe PDF | 見る/開く |
| タイトル: | Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication |
| 著者: | KITO, Nobutaka AKIMOTO, Kazushi TAKAGI, Naofumi    https://orcid.org/0000-0003-0016-7436 (unconfirmed) |
| 著者名の別形: | 鬼頭, 信貴 秋元, 一志 髙木, 直史 |
| キーワード: | concurrent error detection floating-point multiplier duplication truncated multiplier |
| 発行日: | 2017 |
| 出版者: | Institute of Electronics, Information and Communications Engineers (IEICE) |
| 誌名: | IEICE Transactions on Information and Systems |
| 巻: | E100.D |
| 号: | 3 |
| 開始ページ: | 531 |
| 終了ページ: | 536 |
| 抄録: | A floating-point multiplier with concurrent error detection capability by partial duplication is proposed. It uses a truncated multiplier for checking of the significand (mantissa) multiplication instead of full duplication. The proposed multiplier can detect any erroneous output with error larger than one unit in the last place (1 ulp) of the significand, which may be overlooked by residue checking. Its circuit area is smaller than that of a fully duplicated one. Area overhead of a single-precision multiplier is about 78% and that of a double-precision one is about 65%. |
| 著作権等: | © 2017 The Institute of Electronics, Information and Communication Engineers |
| URI: | http://hdl.handle.net/2433/226243 |
| DOI(出版社版): | 10.1587/transinf.2016EDP7158 |
| 出現コレクション: | 学術雑誌掲載論文等 |
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