4H-SiC MIS capacitors and MISFETs with deposited SiNx/SiO2 stack-gate structures

Abstract

SiNx

SiO2 stack-gate structures, followed by N2O annealing, have been investigated to improve the 4H-SiC metal- insulator-semiconductor (MIS) interface quality. Capacitance- voltage measurements on fabricated stack-gate MIS capacitors have indicated that the interface trap density is reduced by post- deposition annealing in N2O at 1300degC. When the MIS capacitor with a SiNx

SiO2 thickness of 10 nm/50 nm was annealed in N2O for 2 h, the interface trap density at Ec - 0.2 eV is below 1 X 1011 cm -2eV-1. Oxidation of SiNx during N2O annealing has resulted in the improvement of SiC MIS interface characteristics, as well as dielectric properties. The fabricated MISFETs with SiNx

SiO2 stack-gate structure annealed in N2O demonstrate a reasonably high channel mobility of 32 cm2

V ldr s on the (0001)Si face and 40 cm2/ V ldrs on the (0001) C face.