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| タイトル: | 4H-SiC MIS capacitors and MISFETs with deposited SiNx/SiO2 stack-gate structures |
| 著者: | Noborio, Masato Suda, Jun  Kimoto, Tsunenobu   https://orcid.org/0000-0002-6649-2090 (unconfirmed) |
| キーワード: | channel mobility deposited insulator interface trap density metal-insulator-semiconductor (MIS) MOSFET silicon carbide (SiC) silicon nitride (SiNx) silicon oxynitride (SiOxNy) |
| 発行日: | Aug-2008 |
| 出版者: | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC |
| 誌名: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
| 巻: | 55 |
| 号: | 8 |
| 開始ページ: | 2054 |
| 終了ページ: | 2060 |
| 抄録: | SiNx SiO2 stack-gate structures, followed by N2O annealing, have been investigated to improve the 4H-SiC metal- insulator-semiconductor (MIS) interface quality. Capacitance- voltage measurements on fabricated stack-gate MIS capacitors have indicated that the interface trap density is reduced by post- deposition annealing in N2O at 1300degC. When the MIS capacitor with a SiNx SiO2 thickness of 10 nm/50 nm was annealed in N2O for 2 h, the interface trap density at Ec - 0.2 eV is below 1 X 1011 cm -2eV-1. Oxidation of SiNx during N2O annealing has resulted in the improvement of SiC MIS interface characteristics, as well as dielectric properties. The fabricated MISFETs with SiNx SiO2 stack-gate structure annealed in N2O demonstrate a reasonably high channel mobility of 32 cm2 V ldr s on the (0001)Si face and 40 cm2/ V ldrs on the (0001) C face. |
| 著作権等: | © 2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. |
| URI: | http://hdl.handle.net/2433/84555 |
| DOI(出版社版): | 10.1109/TED.2008.926644 |
| 出現コレクション: | 学術雑誌掲載論文等 |
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