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| 書誌情報 | ファイル |
|---|---|
| Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element YUASA, Hiroshi; TSUTSUI, Hiroshi; OCHI, Hiroyuki; SATO, Takashi (2013-04) IEICE Transactions on Electronics, E96.C(4): 473-481 |  |
| A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis IMAGAWA, Takashi; TSUTSUI, Hiroshi; OCHI, Hiroyuki; SATO, Takashi (2013-04) IEICE Transactions on Electronics, E96.C(4): 454-462 | |
| Device-Parameter Estimation through IDDQ Signatures SHINTANI, Michihiro; SATO, Takashi (2013-02) IEICE Transactions on Information and Systems, E96.D(2): 303-313 | |