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| 書誌情報 | ファイル |
|---|---|
| Fast estimation of NBTI-induced delay degradation based on signal probability Bian, Song; Shintani, Michihiro; Hiromoto, Masayuki; Sato, Takashi (2016-07-01) IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E99.A: 1400-1409 |  |
| An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs IMAGAWA, Takashi; HIROMOTO, Masayuki; OCHI, Hiroyuki; SATO, Takashi (2015-07) IEICE Transactions on Electronics, E98.C(7): 741-750 | |
| A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis IMAGAWA, Takashi; TSUTSUI, Hiroshi; OCHI, Hiroyuki; SATO, Takashi (2013-04) IEICE Transactions on Electronics, E96.C(4): 454-462 | |
| Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures IMAGAWA, Takashi; HIROMOTO, Masayuki; OCHI, Hiroyuki; SATO, Takashi (2010-12) IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E93-A(12): 2524-2532 | |
| Utilization of Path-Clustering in Efficient Stress-Control Gate Replacement for NBTI Mitigation MORITA, Shumpei; BIAN, Song; SHINTANI, Michihiro; HIROMOTO, Masayuki; SATO, Takashi (2017-07-01) IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E100.A(7): 1464-1472 | |