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書誌情報 | ファイル |
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An Error Correction Scheme through Time Redundancy for Enhancing Persistent Soft-Error Tolerance of CGRAs IMAGAWA, Takashi; HIROMOTO, Masayuki; OCHI, Hiroyuki; SATO, Takashi (2015-07) IEICE Transactions on Electronics, E98.C(7): 741-750 | |
Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element YUASA, Hiroshi; TSUTSUI, Hiroshi; OCHI, Hiroyuki; SATO, Takashi (2013-04) IEICE Transactions on Electronics, E96.C(4): 473-481 | |
A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis IMAGAWA, Takashi; TSUTSUI, Hiroshi; OCHI, Hiroyuki; SATO, Takashi (2013-04) IEICE Transactions on Electronics, E96.C(4): 454-462 | |
Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures IMAGAWA, Takashi; HIROMOTO, Masayuki; OCHI, Hiroyuki; SATO, Takashi (2010-12) IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E93-A(12): 2524-2532 | |
Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method AWANO, Hiromitsu; TSUTSUI, Hiroshi; OCHI, Hiroyuki; SATO, Takashi (2012-12) IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E95.A(12): 2272-2283 | |
A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits KAWASHIMA, Junya; TSUTSUI, Hiroshi; OCHI, Hiroyuki; SATO, Takashi (2012-12) IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, E95.A(12): 2242-2250 |